Chapter 1 : SystemC Overview

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Chapter 1 : SystemC Overview

What is SystemC Systemc is a modeling platform A set C class library to add hardware modeling constructs Simulation kernel Supports different levels of abstraction Untimed Functional Model Transaction Level Model Bus Function Model

Why we need systemc The increasingly shortened time to market requirements Verify the design in early time The growing complexity Integration of devise devices

SystemC Heritage ref : SOCLab 03 SOC Design Flow.pdf, 2004 spring, NCTU

SystemC Design Flow

Using software to simulate hardware behavior Extensions Parallel execution Clock Module concept Interconnection

Example – half adder #include “systemc.h” SC MODULE(half adder) { sc in bool a, b; sc out bool sum, carry; void proc half adder(); SC CTOR(half adder) { SC METHOD (proc half adder); sensitive a b; } }; void half adder::proc half adder() { sum a b; carry a & b; }

Module --- Basic Block Verilog module module name(input/output declaration) variable declaration computation block endmodule SystemC SC MODULE (module name) { input/output declaration internal variable constructor (computation block) };

Input/output Declaration Verilog Input : input var1, ; Output : output var2, ; Type SystemC input : sc in type var1, ; Output : sc out type var2, ; Type C primitive type : int, float, char, . hardware type : sc int, sc uint, . user defined type

Computation Block Verilog Event trigger : always@(a or b or c) Edge trigger : always@(posedge clk) SystemC SC CTOR (module name) { SC METHOD (function name); sensitive a b c; } Sensitivity list C constructor Computation function name

Describing Hierarchy #include “half adder.h” SC MODULE (full adder) { sc in bool a, b, carry in; sc out bool sum, carry out; sc signal bool c1, s2, c2; void proc or(); half adder ha1(“ha1”), ha2(“ha2”); SC CTOR(full adder) { ha1.a(a); //by name connection ha1.b(b); ha1.sum(s1); ha1.carry(c1); h2(s1, carry in, sum c2) //by position connection SC METHOD (proc or); seneitive c1 c2; } };

Main --- Top Module #Include “full adder.h” #Include “pattern gen.h” #include “monitor.h” int sc main(int argc, char* argv[]) { sc signal booL t a, t b, t cin, t sum, t cout; full adder f1(“Fulladder”); sum Full adder carry a //connect using positional association f1 t a t b t cin t sum t cout; pattern gen pg ptr new pattern gen(“Genartion”); //connection using named association pg ptr- d a(t a); pg ptr- d b(t b); (*pg ptr- d cin(t cin); monitor mol(“Monitor”); mo1 t a t b t cin t sum t cout; sc start(100, SC NS); return 0; Monitor b c in Pattern gen

SystemC Installation Download Decompress data to /path/to/destination C:\temp\ systemc-2.0.1\ Open project file sys overview 04f all/lab/systemc-2.0.1.tgz C:\temp\systemc-2.0.1\msvc60\systemc\systemc.dsw Build Build- Build systemclib (F7)

Project compilation Example Decompression File- New- Project- win32 Console application - empty project Add existed files C:\temp Create new project sys overview 04fall/lab/ systemc ex01.rar Project- Add to Project - Files main.c module.c module.h Building argument and dependency C runtime type indentification Include path Link path and libaray

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